View IR3531A-MTRPBF_8115656.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 1 features ? integrated 6.8v/0.8a buck regulator provides bias to control and driver ic(s) ? adjustable switching frequency from 250 khz up to 1.5mhz per phase based on the synchronization sclk input ? sink and source tracking capability ? margining via svid for both rails ? pre - bias compatible ? soft stop capability ? 0.5% overall system set point accuracy ? voltage mode modulation for excellent transient performance ? single ntc thermistor for current reporting, oc threshold, and load line thermal compensation ? complete protection including over - current, over - voltage, over - temperature, open remote sense and open control loop ? thermally enhanced 48l 7 mm x 7 mm mlpq package ? rohs compliant basic application circuit figure 1: ir 3531a basic application circuit , s howing a 4+1 configuration description the ir3531 a control ic provides all the n ecessary control, communication and protection to support compact dual output power solution s up to 210w . the ir 3531a can be combined with either discrete ir3535 d river ic s and direct fets tm or our ir35xx family of footprint compatible and scalable powirstages tm which integrate the mosfets and driver into the same package. the ir 3531a provides overall system control and current sharing while the driver ic or power stages senses per - phase current locally and communicates it to the control ic . the ir 3531a has tri - state pwm outputs to allow diode emulation during light load events. the ir 3531a provides a high performance transient solution through classic voltage mode control and body braking tm . body braking tm automatically turns off the low - side mosfet to help dissipate stored inductor energy at load turn - off. pin diagram figure 2: ir 3531 a package top view a i r 3 5 3 1 a 4 8 p i n 7 x 7 m l p q t o p v i e w 4 9 g n d p w m _ r 1 i i n _ r 1 v d a c 1 v d r p 1 e a 1 v o s e n 1 + t r a c k 1 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 f b 1 v o 1 v o s e n 1 - e n v r h o t # v r r d y 1 v r r d y v c c s w v 1 2 v a l e r t # v c l k v d i o p h s s h e d i m o n _ r 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 b b r 1 # p w m 4 p w m 3 t s e n s r o s c / o v p a d d r i c c p s c l k p w m 2 p w m 1 b b r # t r a c k 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 i i n 4 3 8 i i n 3 3 7 i m o n v d a c v n v d r p e a v o v o s e n - 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 p s c f b v o s e n + i i n 1 2 3 i i n 2 2 4
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 2 ordering information ir 3531a D m ? ? ? ? ? package tape & reel qty part number 48 lead mlpq (7x7 mm body) 1 00 ir 3531a - mpbf 48 lead mlpq (7x7 mm body) 3000 ir 3531a - mtrpbf 1 note 1 : samples only. figure 3: package top view, enlarged pbf C lead free tr C tape and reel i r 3 5 3 1 a 4 8 p i n 7 x 7 m l p q t o p v i e w 4 9 g n d p w m _ r 1 i i n _ r 1 v d a c 1 v d r p 1 e a 1 v o s e n 1 + t r a c k 1 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 f b 1 v o 1 v o s e n 1 - e n v r h o t # v r r d y 1 v r r d y v c c s w v 1 2 v a l e r t # v c l k v d i o p h s s h e d i m o n _ r 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 b b r 1 # p w m 4 p w m 3 t s e n s r o s c / o v p a d d r i c c p s c l k p w m 2 p w m 1 b b r # t r a c k 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 i i n 4 3 8 i i n 3 3 7 i m o n v d a c v n v d r p e a v o v o s e n - 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 p s c f b v o s e n + i i n 1 2 3 i i n 2 2 4
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 3 functional block dia gram figure 4 : ir 3531a block diagram
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 4 typical application diagram figure 5 : ir 3531a typical application diagram cimon1 vosen1- vosen1+ vdac to iout signals of phases 1, 2 bbr# pwm1 pwm2 raddr1 track1 rpsc rfb1 to pwm signals of phases 1, 2 pwm3 riccp1 12v rhotset1 vdac cfb1 1 2 lvcc enable coutvcc alert# 8 vclk 9 vdac 14 v12v 7 ea 17 pwm1 27 phsshed 11 vcc 5 iin2 24 vosen- 22 track 25 imon 13 vdrp 16 sclk 29 bbr# 26 vn 15 fb 19 pwm2 28 vo 20 vosen+ 21 vo1 42 vosen1+ 41 vosen1- 40 track1 39 iin4 38 bbr1# 36 pwm4 35 pwm3 34 tsens 33 rosc/ovp 32 addr 31 iin3 37 fb1 43 ea1 44 vdrp1 45 vdac1 46 iin_r1 47 vrhot# 2 vrrdy 4 vdio 10 pwm_r1 48 en 1 vrrdy 1 3 psc 18 iin1 23 iccp 30 imon_r1 12 gnd 49 sw 6 ir3531a vrhot# vrrdy vclk vdio rcfb1 cea cfb alert# rtcmp1 rdrp rfb vosen+ rtcmp3 rcfb vosen- vrrdy 1 rtcmp2 rtherm1 rtherm2 rosc rcp cea1 raddr2 ccp rhotset2 riccp2 rhotset3 ccp1 rcp1 iin1 iin2 to pwm signals of phases 3, 4 to iout signals of phases 3, 4 iin3 vdac rdrp1 rail1 signals track phsshed pwm4 sclk iin4 rtherm3 rscale1 rscale3 rscale2 bbr1# vdac1 cimon pwm_r1 iout1
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 5 pin descriptions pin # pin name pin description 1 en enable input. grounding this pin shuts down the voltage regulators. do not float this pin as the logic state will be undefined. 2 vrhot# open collector output of the vrhot# comparator which drives low if rail0 temperature exceeds the programmed threshold. connect external pull - up to bias. 3 vdrry1 open collector output that drives low during startup and under any external fault condition for rail1 regulator. connect external pull - up to bias. 4 vdrry open collector output that drives low during startup and under any external fault condition for rail0 regulator. connect external pull - up to bias. 5 vcc bias buck regulator output, feedback pin, and bias input for internal circuitry. 6 sw switching node for bias buck regulator. 7 v12v power supply input supply rail. 8 alert# output pin for svid alert# interrupt. open collector output that drives low to notify the master. 9 vclk svid clock input. clock is a high impedance input pin. it is driven by the open collector output of a microprocessor and requires a pull - up resistor. 10 vdio svid data input/output. high impedance input when address, command or data bits are shifted in, open drain output when acknowledging or sending data back to the microprocessor. pin requires a pull up resistor. 11 phsshed analog signal that represents the number of phases to be disabled. 0% to 25% vcc, no phases disabled. 25% to 50% vcc, disable 1 phase. 50% to 75% vcc, disable 2 phases. 75% to 100% vcc, disable 3 phases (if available). 12 imon_r1 voltage at this pin is proportional to rail1 load current. it is also the input to the adc for output current register. 13 imon voltage at this pin is proportional to rail0 load current. it is also the input to the adc for output current register. 14 vdac voltage regulator rail 0 reference voltage programmed by svid. vdac is also used as the a/d reference during power up for pins addr/psn, tsens and iccp. 15 vn node for dcr thermal compensation network. 16 vdrp buffered, scaled and thermally compensated current signal for rail0. connect an external resistor to fb to program converter output impedance. 17 ea output of the error amplifier for rail0. 18 psc node for power savings mode compensation input. 19 fb inverting input to the error amplifier for rail0. 20 vo remote sense amplifier output for rail0. 21 vosen+ rail0 remote sense amplifier input. connect to output at the load. 22 vosen - rail0 remote sense amplifier input. connect to ground at the load. 23, 24, 37, 38 iin1 - 4 current signals from the driver ic - s of rail0. 25 track external tracking reference for rail0 . 26 bbr# body - braking tm bus for rail0 driver ics to disable synchronous switches. 27, 28, 34, 35 pwm1 - 4 pwm outputs for rail0. each output is connected to the input of the driver ic. connecting the pwmx output to lgnd disables the phase, allowing the ir 3531a to operate as a 1, 2, 3, or 4 phase controller. 29 sclk synchronization clock input. program rosc using rosc vs. frequency to match the sclk frequency .
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 6 pin # pin name pin description 30 iccp program maximum load current for both rail0 and rail1. 31 addr programs svid address for rail0 and rail1 . 32 rosc/ovp connect a resistor to lgnd to program oscillator frequency. oscillator frequency equals switching frequency per phase. rosc/ovp pin is pulled up to vcc when an over voltage event occurs. 33 tsens pin for thermal network that senses the temperature of rail0 and rail1. 36 bbr1# body - braking tm bus for rail1 driver ics to disable synchronous switches. 39 track1 external tracking reference for rail1. 40 vosen1 - rail1 remote sense amplifier input. connect to ground at the load. 41 vosen1+ rail1 remote sense amplifier input. connect to output at the load. 42 vo1 remote sense amplifier output for rail1. 43 fb1 inverting input to the error amplifier for rail1. 44 ea1 output of the error amplifier for rail1. 45 vdrp1 buffered, scaled and thermally compensated current signal for rail1. connect an external resistor to fb1 to program converter output impedance. 46 vdac1 buffered rail1 reference voltage. voltage can be margined via svid. 47 iin_r1 current signal from rail1 driver ic. 48 pwm_r1 pwm output for rail1. 49 gnd local ground for internal circuitry and ic substrate connection.
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 7 absolute maximum rat ings storage temperature range - 6 5c to 150c operating junction temperature 0c to 150c esd rating hbm class 1c jedec standard msl rating 2 reflow temperature 260 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rati ngs only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. pin number pin name v max v min i s ource i sink 1 en 3.5v - 0.3v 25m a 1m a 2 vrhot# vcc - 0.3v 1m a 50m a 3 vdrry1 vcc - 0.3v 1m a 20m a 4 vdrry vcc - 0.3v 1m a 20m a 5 vcc 8v - 0.3v 1m a 20m a 6 sw 16 v - 1.0 v 3 a 1m a 7 v12v 16 v - 0.5 v 1m a 1.5 a 8 alert# 3.5 v - 0.3v 1m a 50m a 9 vclk 3.5 v - 0.3v 1 ma 1m a 10 vdio 3.5 v - 0.3v 1m a 50m a 11 phsshed vcc - 0.3v 1ma 1ma 12 imon_r1 3.5v - 0.3v 25m a 1m a 13 imon 3.5v - 0.3v 25ma 1m a 14 vdac 3.5 v - 0.3v 5ma 35ma 15 vn vcc - 0.3v 1m a 1m a 16 vdrp vcc - 0.3v 35m a 1m a 17 ea vcc - 0.3v 35m a 5m a 18 psc vcc - 0.3v 1m a 1m a 19 fb vcc - 0.3v 1m a 1m a 20 vo vcc - 0.3v 35ma 5m a 21 vosen+ vcc - 0.5v 5ma 1m a 22 vosen - 1.0v - 0.5v 5ma 1m a 23 iin1 vcc - 0.3v 1m a 1m a 24 iin2 vcc - 0.3v 1m a 1m a 25 track vcc - 0.3v 1m a 1m a 26 bbr# vcc - 0.3v 1m a 5m a 27 pwm1 vcc - 0.3v 1m a 5m a
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 8 pin number pin name v max v min i s ource i sink 28 pwm2 vcc - 0.3v 1ma 5ma 29 sclk 3.5v - 0.3v 1ma 5ma 30 iccp 3.5v - 0.3v 1ma 1ma 31 addr 3.5v - 0.3v 1ma 1ma 32 rosc vcc - 0.3v 1ma 1ma 33 tsen 3.5v - 0.3v 1ma 1ma 34 pwm3 vcc - 0.3v 1ma 5ma 35 pwm4 vcc - 0.3v 1ma 5ma 36 bbr1# vcc - 0.3v 1ma 5ma 37 iin3 vcc - 0.3v 1ma 1ma 38 iin4 vcc - 0.3 v 1ma 1ma 39 track1 vcc - 0.3 v 1ma 1ma 40 vosen1 - 1.0v - 0.5 v 5ma 1ma 41 vosen1+ vcc - 0.5 v 5ma 1ma 42 vo1 vcc - 0.5 v 35ma 5ma 43 fb1 vcc - 0.3v 1ma 1ma 44 ea1 vcc - 0.3v 35ma 5ma 45 vdrp1 vcc - 0.3v 35ma 1ma 46 vdac1 3.5v - 0.3v 1ma 35ma 47 iin_r1 vcc - 0.3v 1ma 1ma 48 pwm_r1 vcc - 0.3v 1ma 1ma 49 gnd n/a n/a 20ma 1ma
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 9 electrical specifications recommended operatin g conditions for relia ble operation with m argin the electrical characteristics table lists the spread of values guaranteed within the recommended operating conditions. typical values represent the median values, which are related to 25c. unless otherwise sp ecified, these specifications apply over: - 0.3v vosen - 0.3v, 7.75k rosc 50.0 k recommended v12v range 10.8v 12 13.2v v recommended vcc range 6.6 6.8 7.0 v vosen - and vosen1 - to lgnd offset - 0.3 0 0.3 v rosc resistor programming range 7.75 50 k recommended operating junction temperature 0 t j 100 oc e lectrical characteri stics parameter symbol conditions min typ max unit vdac reference system set - point accuracy setacc v id 1v - 0.5 - 0.5 % 0.8 vid < 1v - 5 - +5 mv 0.25v vid < 0.8v - 8 - +8 mv slew rate C f ast m ode vidfast 15 20 25 mv/ s slew rate C s low m ode vidslow 3.75 5 6.25 mv/ s default vboot rail 0 vboot0 note 3 - 1.5 - v default vboot rail 1 vboot1 note 3 - 1.5 - v oscillator (note 4) rosc voltage vrosc rosc = 24.5 k 0.570 0.595 0.62 0 v pwm frequency fswmin rosc = 50.0 k - 250 - khz fswtyp rosc = 24.5 k - 500 - khz fswmax rosc = 7.75 k - 1.50 - mhz vdac buffer amplifier input outset voltage dacoff v(vdac, vdac1) D vid code + vid offset, 0.25v v(vdac, vdac1) 1.52v, < 1ma load - 15 0 15 mv source current dacsrc 0.25v v( vdac 1 ) 1 .52v 0.3 0.44 0.6 ma 0.25v v( vdac ) 1 .52v 0.9 1. 6 5 2. 4 sink current dacsnk 0.5v v( vdac 1 ) 1.52v 2 13 20 ma v( vdac1 ) = 0.25v 0.5 1.5 2 0.5v v( vdac ) 1.52v 3 1 5 30 v( vdac ) = 0.25v 0.5 1.5 3
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 10 parameter symbol conditions min typ max unit unity gain bandwidth - 3.5 - mhz slew rate - 1.5 - v/ s thermal compensation amplifier (vdrp) output offset voltage vdrpoutoff 0v v(iin) C v(vdac) 1 .52v , 0.25v v(vdac) 1.52v, req/r2 = 2 - 14 0 14 mv source current vdrpsrc 0.25v v(vdac) 1 .52v 3 8 15 ma sink current vdrpsnk 0.5v v(vdrp) 1 .52v 0. 2 0.4 0. 7 ma v(vdrp) = 0.25v 0.175 0.25 0. 4 unity gain bandwidth req/r2 = 2 , note 1 2 4.5 7 mhz slew rate - 5.5 - v/ s vn bias current v(vn) = 2 v - 2 0 2 a power savings mode operation ps2/ps3 turn - o n threshold ps2thrsh vid = 250 mv 250 350 385 mv vid = 1.52 v 2 2.15 2.2 6 v ps2/ps3 pulse width rail0 ps2cot0 vid = 25 0 mv, sf = 5 00 khz 6 0 151 200 ns vid = 1.52 v, sf = 5 00 khz 220 409 48 0 ps2/ps3 pulse width rail1 ps2cotmin1 vid = 250 mv, sf = 5 00 khz 5 0 100 20 0 ns ps2cotmax1 vid = 1.52 v, sf = 5 00 khz 220 358 48 0 ps mode enter delay ps1delay ps0 to ps1 only - 8 - pwm cycle enable input rising threshold enrise 625 650 675 mv falling threshold enfall 575 600 625 mv hysteresis enhyst 25 50 75 mv bias current enbias 0v v(enable) 3.3v - 5 0 5 a blanking time noise pulse < 100ns will not register an enable state change. note 1 75 250 400 ns imonx current report amplifier output offset voltage imonoff v drp C v dac = 0, 225, 450, 900mv 15 50 90 m v unity gain bandwidth note 1 - 1 - mhz input filter time constant - 1 - s max output voltage imonmax 1.0 0 1.09 1.145 v current report a/d accuracy imonacc v drp C v dac = 900mv - 2 0 2 % rail1 vdrp amplifier output outset voltage vdrp1off 0 v v( iin_r1 ) - v( vdac1) 0. 2v 0.25v v(iin_r1) - v( vdac1) 1.52 v - 75 0 75 mv
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 11 parameter symbol conditions min typ max unit source current vdrp1src 0.25v v(vdac1) 1.52 v 3 8 15 ma sink current vdrp1snk 0.5v v( vdrp1 ) 1.52 v 0. 2 0.4 0. 6 ma v( vdrp1 ) = 0.25v 0.175 0.25 0.37 5 closed loop gain note 1 - 9 - v/v unity gain bandwidth note 1 0.8 1.5 3 mhz slew rate note 1 - 5.5 - v/s error amplifier input offset voltage note 2 (test mode only) - 0 - mv fb bias current - 1 0 1 a dc gain note 1 100 110 120 db unity gain bandwidth note 1 20 30 40 mhz slew rate note 1 7 12 20 v/s sink current easrc 0.40 0.85 1. 35 ma source current easnk 5 8 12 ma maximum voltage eamax measure v(vcc ) C v(ea) , v(ea1) 500 925 110 0 mv minimum voltage eamin - 120 250 mv open voltage loop detection threshold eaopenthr measure v(vccx) - v(ea), v(ea1), relative to error amplifier maximum voltage 100 300 1100 mv open loop detection delay eaopendel v(ea) , v(ea1) = v(vcc ) to vrrdy = low - 8 - pwm ps2 clamp voltage eaps2clmp w ith respect to vdac - 240 - 70 - 1 0 mv phase firing comparators input offset keepoff - 30 0 30 mv propagation delay keepdel - - 32 0 ns phase shedding comparators bias current phsdbias - 2 0 2 a threshold phsdthrs comparator 1 1. 3 1.7 2.0 v comparator 2 3. 0 3.4 3. 85 comparator 3 4.8 5.1 5. 55 pwm comparator pwm ramp slope pwmslp v12v= 12v 42 52.5 57 mv/ %dc minimum pulse width pwmmin note 1 55 70 ns input offset voltage pwmoff note 1 - 5 0 5 mv share adjust amplifier input offset voltage saaoff note 1 - 3 0 3 mv gain saagain csin+ = csin - = dacin, note 1 4 5.0 6 v/v unity gain bandwidth note 1 4 8.5 17 khz
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 12 parameter symbol conditions min typ max unit maximum pwm ramp floor voltage minfloor iout = dacin C 200mv measure relative to floor voltage 100 180 22 0 mv minimum pwm ramp floor voltage maxfloor iout = dacin + 200mv measure relative to floor voltage - 220 - 160 - 100 mv over voltage protection (ovp) co m parators threshold at power - up ovppup 1. 615 1. 65 1. 67 v threshold during normal operation ovpthr compare to vid voltage + vid offset 10 0 130 150 mv propagation delay to ovp ovpprop measure time from v(fb), v(fb1) > vid voltage + vid offset (250mv overdrive) to v(pwm) transition to > 0.5 * v(vcc) - 90 180 ns over - current comparator input filter time constant - 2 - s over - current threshold octhrsh vdrp - vdac, vdrp1 - vdac1 0.9 4 1.08 1.18 v oc threshold psi r eduction f actor ocpsi psi mode, 4ph to 2ph, 2ph to 1ph 4 5 0 540 610 mv psi mode, 3ph to 1ph 310 360 410 3 ph to 2ph 640 720 800 psi mode, 4ph to 1ph 220 270 310 4 ph to 3 ph 690 800 900 oc delay time ocdelay delay to oc shutdown 225 256 285 s vcc undervoltage vcc uvl start vccstart 5.5 5.85 6. 4 v vcc uvl stop vccstop 4.8 5 5.2 5. 65 v vcc uvl hysteresis vcchyst 515 650 830 mv vrrdy output output voltage vrrdylo i(vrrdy, vdrry1) = 4ma - 150 300 mv leakage current vrrdyleak v(vrrdy, vdrry1) = 5.5v - 0 10 a vcc activation voltage vrrdyvcc i(vdrry, vdrry1) = 4ma, <300mv 1 2 3.6 v vo - track undervoltage threshold vouvfall reference to track - 260 - 20 0 - 130 mv vo - vdac undervoltage threshold vouvrise reference to vdac - 34 0 - 29 0 - 230 mv open sense line detection sense line detection active comparator threshold voltage openact 100 150 200 mv sense line detection active comparator offset voltage openoff v(vo) < [v(vosen+) C v(lgnd)] / 2 25 60 8 0 mv vosen+ open sense line comparator threshold opencomp+ compare to v(vcc) 8 2 90 92 %
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 13 parameter symbol conditions min typ max unit vosen - open sense line comparator threshold opencomp - 0.36 0.40 0.44 v sense line detection source currents opensrc v(vo) = 100mv 200 500 700 a vcc buck regulator vcc output voltage vcc100 100 C 400 ma load current 6.5 6.8 7.1 v switch node rise time swrise note 1 - 5 - ns switch node fall time swfall note 1 - 15 - ns a/d program inputs addr pin bias current addrbias - 2 0 2 a iccp pin bias current iccpbias - 2 0 2 a tsens pin bias current tsenbias - 2 0 2 a a/d comparator offset adoffset - 5 0 5 mv v12v undervoltage vcc v12v start vccstart 8.8 9.6 10.2 v vcc v12v stop vccstop 7. 8 8.6 9.2 v vcc v12v hysteresis vcchyst 0.8 1 1. 3 v serialvid alert#, vdio buffer on resistance alertres - - 14.3 ? alert#, vdio leakage current alertleak - 10 0 10 a vclk bias current vclkbias - 1 0 1 a vdio bias current vdiobias - 1 0 1 a transmit data prop delay xmitdelay vclk rising to vdio change 4 6 12 ns comparator threshold svidthrsh vclk , vdio rising 500 590 650 mv vclk, vdio falling 450 515 65 0 comparator hysteresis svidhyst 50 75 - mv link states reset timer svidtime 200 - 600 ns pwmx outputs source resistance pwmsrcr 50 144 500 ? sink resistance pwmsnkr 75 117 29 0 ? tri - state source impedance pwmtriz 2.0 5.4 7.5 k? tri - state bias current pwmtribias v(pwmx) = 1.65v - 5 0 5 a tri - state active pull - up pwmtripup v(pwmx) while sourcing 100 a to gnd 0. 5 1 1. 2 v disable comparator threshold pwmdisthr 0.4 0.6 0. 9 v pwm high voltage pwmhigh i(pwm) = - 1ma, measure vcc - pwm - - 1 v
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 14 parameter symbol conditions min typ max unit pwm low voltage pwmlow i(pwm) = - 1ma - - 1 v body braking comparator threshold voltage with eain d ecreasing bbrthrfall measure relative to floor voltage - 300 - 200 - 110 mv threshold voltage with eain i ncreasing bbrthrrise measure relative to floor voltage - 200 - 100 - 10 mv hysteresis bbrthrhys 70 105 130 mv propagation delay bbrdelay vcc = 5v measure time from eain < v(dacin) (200mv overdrive) to gatel transition to < 4v. 30 65 90 ns bbr 1 # source resistance bbrsrcres 20 40 75 ? bbr 1 # sink resistance bbrsnkres 10 35 60 ? bbr 1 # high voltage bbrhigh i(bbr 1 #) = - 1ma, measure v(vcc) C v(bbr 1 #) 0 0.4 0.8 v bbr 1 # low voltage bbrlow i(bbr 1 #) = 1ma 0 0.35 0.8 v remote sense differential amplifier unity gain bandwidth rsabw note 1 1.5 3.2 4.5 mv input outset voltage rsaoff 0.25v v(vosen+) - v(vosen - ) 1.52v , 0.25v v(vosen 1 +) - v(vosen 1 - ) 1.52v - 5 0 5 mv sink current rsasink 0.5v v(vosen+) - v(vosen - ) 1.52v , 0.5v v(vosen 1 +) - v(vosen 1 - ) 1.52v 0.4 1 2 ma v(vosen+) - v(vosen - ) = 0.25v , v(vosen 1 +) - v(vosen 1 - ) = 0.25v 0.225 0.5 0.8 source current rsasrc 0.25v v(vosen+) - v(vosen - ) 1.52v , 0.25v v(vosen 1 +) - v(vosen 1 - ) 1.52v 3 9 20 ma slew rate rsaslew 0.25v v(vosen+) - v(vosen - ) 1.52v , 0.25v v(vosen 1 +) - v(vosen 1 - ) 1.52 v 2 4 8 v/s vosen+ bias current vosns - bias 0.25 v < v(vosen+) < 1.52v , 0.25 v < v(vosen 1 +) < 1.52v - 27 50 a vosen - bias current vosns+bias - 0.3v vosen - 0.3v, all vid codes , - 0.3v vosen 1 - 0.3v, all vid codes - 27 7 0 a high voltage vohigh v(vcc ) C v(vo) , v(vcc) C v(vo1) 1.5 2 2.5 v low voltage volow v(vcc ) = 7v - 60 100 mv vrhot# comparator
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 15 parameter symbol conditions min typ max unit output voltage vrhtout i(vrhot # ) = 30ma - 150 400 mv vrhot# leakage current vrhtleak v (vrhot # ) = 5.5v - 0 10 a platform test mode comparator t hreshold ptmthr raise addr voltage after vin power - up 2.2 2.6 3.1 v link states reset timer ptmtime 20 - 24 s vr settled comparator offset vrstloff compare fb to vdac reference - 20 - mv delay to alert# vrstldelay delay after dac settled to within 2 vid steps of final value - 5 - s current inputs iinx to iinx impedance iinres - 3000 - ? iinx to iinx leakage current iinleak - 1 0 1 a track inputs input leakage - 1 0 1 a track to fb offset error amp in unity gain 15 36 65 mv release error voltage track = vdac+100mv, vdac - fb - 1 0 1 mv vo discharge comparators tri - state enable threshold vo when pwm outputs enter tri - state 200 250 300 mv sclk synchronization input rising threshold 0.8 1.2 1.3 v falling threshold note 1 0.625 0.85 1.025 v input leakage - 5 0 5 a propagation delay rising - - 60 ns input capacitance note 1 - - 10 pf general vcc supply current vccbias 3 7 12 ma notes : 1 . guaranteed by design but not tested in production 2 . error amplifier input offset is trimmed to within 1% for optimal system set point accuracy. 3. final test vboot options of 0, 0.9, 1. 35 and 1.5 v are feasible. contact international rectifier enterprise power business unit for details. 4. use sclk input to set pwm frequency.
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 16 theory of operation system description the ir 3531a multiphase buck power system provides voltage regulation solutions for two individual supply outputs. the main output, rail0, controls up to four phases and produce up to 200a when paired with appropriate power stages. the secondary output, rail1, is a si ngle phase output capable of up to 50a, again with appropriate power stage. the ir 3531a control ic is specialized to allow external clock synchronization and tra cking capability for each rail. features include a serial control and telemetry bus that can co ntrol output voltage settings and slew rates while allowing monitoring of the system thermals and load curr ents. the ir 3531a control ic contains all necessary housekeeping, protection and control functions and communicates a three - level pwm signal to each power stage . frequency and phase timing control the ir 3531a requires external frequency synchronization which can be used to control input ripple from multiple pa ralleled power supply systems. systems can be forced to operate out of phase thereby reducin g instantaneous peak input currents and also contro lling system noise signatures. the internal oscillator is used to calibrate the pwm ramp slopes and other functions at power up therefore it is desirable for the externally applied synchronization frequenc y to be very near the rosc programmed internal frequency tim es the number of active phases. c alibration can take up to 1ms. this results in the pwm gain to be near the desired 50mv/% duty cycle. furthermore, it is desired the sclk input be stable prior to enabling the ir 3531a voltage regulator. the sclk input frequency provided needs to equal the desired base switching frequency multiplied b y the active number of phases. phase shedding is available however sclk needs to be adjusted accordingly to match th e number of active phases. the system clock frequency has a programmable range from 250khz to 9mhz selected by an external resistor from the rosc pin to ground. phase timing and interleave spacing is automatically optimized inside the controller and can accommodate changing phase s on the fly (phase shedding). the phsshd pin can be used to dynamically drop from 1 - 3 phases while minimizing output voltag e transients. also, phases can be disabled by grounding the pwm outputs of the ir 3531a . notice the driver ics should be removed since a pwm low signal indicates a 0% duty cycle state which turns on the low side mosfets and can potentially develop large ne gative inductor currents. the control ic detects which pwm pins are grounded during power up to determine the populated number of phases and automatically optimizes phase timing for minimal system ripple . track functionality both rail outputs of the ir 3531a can be independently controlled through their respective track inputs. track pins override the internal vdac reference inputs to the error amplifiers allowing users to control power up and power down vr output voltage characteristics. the ir 3531a is fully sof t - stop and pre - bias compatible. the control loop is full synchro nous during soft stop events thereby preventing cout capacitor discharge - induced inductive kicks. the control system allows non - synchronous buck operation once vo <=250mv D this figure 6: track operation with pre - bias
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 17 figure 7: track operation without pre - bias allows outputs to return to their pre - biased operating points if available. the track inputs have a typical 36mv offset from the closed loop feedback operating point to ensure the error amplifi er is in an off state when track=0v. furthermore, track must exceed the respective vdac by at least 100mv to ensure vdac has complete control of the error amplifier as shown in figures 6 and 7 . as a cautionary note the track input provides direct control o f the output pwm duty cycle. the presence of excessive noise or glitches on track when this input is active can cause sudden increases in the pwm duty cycle (up to 100%), potentially causing damage to the power converter. pwm control method the steady stat e control architecture utilized in the ir 3531a is feed - forward voltage mode control with trailing edge modulation. a high - gain wide - bandwidth voltage type error amplifier is used to achieve accurate voltage regulation and ultra - fast transient response. fee d - forward control is established by varying the pwm ramp slope proportionally to the input voltage resulting in the error amplifier operating point being independent of the input voltage. the input voltage can change due to variations in the silver box out put voltage or due to the wire and pcb - trace voltage drop relat ed to changes in load current. all pwm ramp slopes are calibrated at initial power - up. the pwm pulse is terminated once the pwm ramp exceeds the error amplifier output voltage. under dynamic load transitions, the ir 3531a utilizes our patented body braking tm algorithm allows all low - side mosfets to be turned off during a load relaxation event allowing the mosfet body diodes to conduct and dissipate some of the stored inductor energy and also sp eed up the inductor current slew rate by introducing a larger voltage across the inductor. body braking tm reduces the peak overshoot of the converter. an error amplifier output voltage greater than the common mode input range of the pwm comparator results in 100% duty cycle regardless of the voltage of the pwm ramp. the resulting pwm control loop is capable of transitioning from 0% duty cycle to 100% dut y cycle with overlapping phases within a few tens of nanoseconds in response to a load step decrease. figure 8 on the next page depicts pwm operating waveforms under various conditions . b ody braking tm in a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load - step de crease is: the slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a loa d - step decrease. the switch node voltage is then forced to decrease until conduction of the synchronous rectifiers body diode occurs. this increases the voltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the cu rrent in the inductor in response to a load transient decrease is now: o min max slew v i i l t ) ( * ? ?
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 18 since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate can be increased significantly. this patented figure 8: pwm operating waveforms technique is referred to as body braking and is accomplished through the body braking comparator . if the error amplifiers output voltage drops below vdac , th is comparator turns off the low - side gate driver, enabling the bottom fet body diode to take over. there is 100mv upslope and 200mv down slope hysteresis for the body braking comparator. lossless average ind uctor current sensing inductor current can be sensed by connecting a series res istor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in figure 8 . the equ ation of the sensing network is: usually the resistor rcs and capacitor ccs are chosen, such th at, the time constant of rcs and ccs equals the time constant of the inductor, which is the inductance l over the inductor dcr r l . if the two time constants match, th e voltage across ccs is proportional to the current through l, and the sense circuit can b e treated as if only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac co mponent of the inductor current. figure 9 : inductor current sensing and current sense amplifier the advantage of sensing t he inductor current versus high - side or low - side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. the outpu t voltage can be positioned to meet a load line based on real - time information. except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. other methods provide no information d uring either load increase (low - side sensing) or load decrease (high - side sensing). an additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak - to - average errors. these errors will appe ar in many ways but one example is the effect of frequency variation. if the frequency of a parti cular unit is 10% low, the peak - to - peak inductor current will be 10% larger and the output impedance of the converter will drop phase clock pulse floor eain pwmrmp gatel gateh duty cycle decrease due to v12v increase (feed - forward) duty cycle increase due to load increase steady - state operation steady - state operation duty cycle decrease due to load decrease (body braking) ot fault (vcc uv, ocp, vid fault) bodydiode o min max slew v v i i l t ? ? ? ) ( * cs cs l l cs cs l c c sr sl r s i c sr s v s v ? ? ? ? ? 1 ) ( 1 1 ) ( ) (
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 19 by about 10%. variations in ind uctance, current sense amplifier bandwidth, pwm prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak - to - average errors . current sense amplif ier a high speed differential current sense amplifier is l ocated in our driver ic s, as shown in figure 9 . its gain is nominally 32.5 over the entire temperature operating range therefore the 3850 ppm/oc inductor dcr temperature coefficient should be compensated in the voltage loop feedback path. this can be accur ately compensated by using a linearized negative tc resistor network where the ntc can be located near the output inductors. the resulting temperature compensated current information is used by the control ic for voltage positioning and current reporting , and over current limit protection. the input offset of this amplifier is calibrated to within +/ - 450 v (6 sigma limits) with a 200uv typical lsb calibration bit. this calibration routi ne is continuous and occurs at every 56 pwm cycles. the current sen se amplifier can accept positive differential input up to 50mv and negative up to - 10mv before clipping. the output of the current sense amplifier is summed with the vdac voltage and is returned to the control ic through the iin pin. the iin pins in the co ntrol ic are internally tied together through 3 kohm resistors to produce a voltage representative of the average phase inductor current . average current shar e loop a current sharing loop i s also incorporated in the ir 3531a to ensure balance between the multiphase buck power stages. poor current sharing can hamper transient response and degrade overall system efficiency. the current information of each phase is compared against the average phase current through a share adjust amplifier which then manipu lates the respective pwm ramp start voltage to add or subtract pwm output duty cycle. the current share amplifier is internally compensated such that the crossover frequency of the current share loop is much slower than that of the voltage loop an d the tw o loops do not interact. instanta neous current balanc e a form of coarse current sharing is also incorporated into the ir 3531a to protect against synchronized high load repetition rate transients which can saturate induc tors and cause ovp conditions. the ph ase firing order of the multiphase system is continually being re - assessed and adjusted if required on a cycle - by - cycle basis to prevent instantaneous phase currents from deviating from each other. this also improves transient response by ensuring all phas e currents track each other within a few switching cycles. individual switch nodes will appear to be variable frequency however input and output ripple are unaffected by the varying phase firing order. svid control the svid bus allows the processor to communicate with the ir 3531a . the processor can program the voltage regulator output voltage and monitor telemetry data the ir 3531a offers such as temperature and both rail currents. vclk , vdio and alert# communication lines are designed for external 50 - 75 ohm pull up resistors to 1.0 - 1.2v bias voltage and should not be floated. note that alert# may assert twice for vid transitions of 2 vid steps or less . addressing is programmed as a percentage of vdac as shown by selecting the appropriate addr pin resisto r divider combination and supports up to 14 addresses and 2 all call addresses (refer to table 1). table 2 provides a li st of supported svid commands. table 3 provides a list of supp orted required svid registers. the svid communi cates vid codes listed in table 4 a and 4b to program the vdac set point. the ir 3531a can accept changes in the vid code and will vary the vdac voltage accordingly. the slew rate of the voltage at the vdac pin can be set by the appropriate command. the slew rate is internally progra mmed and no external pins or components are necessary. digital vid transitions result in a smooth analog transition of the vdac voltage and converter output voltage minimizing inrush currents, false over current conditions and overshoot of the output volta ge. the vid data from the svid bus is stored in registers and is sent to the digital - to - analog converter (dac), whose output is sent to the vdac buffer amplifier. the output of the buffer amplifier is the vdac pin. to achieve optimal system setpoint volt age accuracy, first all contributing offsets of the ir 3531a are independently trimmed and lastly the internal vdac reference is trimmed to take into account all sum of all the offset components. note that the resulting final vdac voltage will have a slight ly wider tolerance as it is compensating for the sum of all other offset components. this results in an overall 0.5% system set - point accuracy for vid range between 1v to 1.52v.
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 20 t able 1: addr a/d v oltage p rogramming ( as % of vdac) % of vdac address name 6.25% a0/a1 21.88% a2/a3 34.38% a 4 /a 5 46.88% a 6 /a 7 59.38% a 8 /a 9 71.88% a 10 /a 11 84.38% a 1 2/a 1 3 note: a14/ a15 are reserved all - call address. svid command structu re svid proto col has two main command groups: the get an d set commands. the get commands retrieve data from the voltage regulator controller, while the set commands make changes to voltage regulator operating points and power states. when the processor (master) issues a get command , it transmits the intended controller address and the address of the register it wants to read. the addressed controller acknowledges the command a nd returns the requested data. similarly, when the processor issues a set command , it transmits the intended controller address and the data it wants to insert. the only exception is the setregadr command which is used to declare the register addr ess that setregdat will alter. the controller acknowledges these commands. parity checking is not enforced on setregad r/ setregdat. t able 2: s upported c ommand command description setvidfast slews vout to a new programmed setpoint at 20mv/usec setvidslow slews vout to a new programmed setpoint at 5mv/usec setps sets power state setregadr declares the address of the register to be written to setregdat writes data to the setregadr declared register getreg read data of a specified register testmode test mode is used for final test trimming of the ir 3531a and is not available to users. note: set vid decay is not supported. t able 3: s upported r egister register description vendorid identifies the vr vendor productid identifies the product model productrev identifies the product revision svid protocol id identifies the version of svid protocol vr capability communicates functions the ir 3531a supports status1 reg stores vr status data status2 reg stores svid bus errors temp zone temperature zone from rail0 sensor output current stores output current for rail0/rail1 status2_last_read stores previous data of status 2 icc max programs the maximum supported output current temp max programs maximum operating temperature sr - fast stores the fast slew rate value sr - slow stores the slow slew rate value vboot overrides the default vboot value vout max programs the maximum supported operational vout vid setting register contains the current vid setting power state register contains the current power state vid offset 1 allows margining around the vid setpoint multi vr config configures other vr - s on the same svid bus setregadr scratch pad register for temporary storage of the setregadr pointer register note 1 : vid offset commands that attempt to push the vid above 1.52v or below 0v are not acknowledged.
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 21 t able 4 : vid values vid7:vid0 (hex) vid 7:vid0 ( bin ) voltage vid7:vid0 (hex) vid 7:vid0 ( bin ) voltage vid7:vid0 (hex) vid 7:vid0 ( bin ) voltage 00 00000000 0 26 00100110 0.435 4c 01001100 0.625 01 00000001 0.25 0 27 00100111 0.44 0 4d 01001101 0.63 0 02 00000010 0.255 28 00101000 0.445 4e 01001110 0.635 03 00000011 0.26 0 29 00101001 0.45 0 4f 01001111 0.64 0 04 00000100 0.265 2a 00101010 0.455 50 01010000 0.645 05 00000101 0.27 0 2b 00101011 0.46 0 51 01010001 0.65 0 06 00000110 0.275 2c 00101100 0.465 52 01010010 0.655 07 00000111 0.28 0 2d 00101101 0.47 0 53 01010011 0.66 0 08 00001000 0.285 2e 00101110 0.475 54 01010100 0.665 09 00001001 0.29 0 2f 00101111 0.48 0 55 01010101 0.67 0 0a 00001010 0.295 30 00110000 0.485 56 01010110 0.675 0b 00001011 0.3 00 31 00110001 0.49 0 57 01010111 0.68 0 0c 00001100 0.305 32 00110010 0.495 58 01011000 0.685 0d 00001101 0.31 0 33 00110011 0.5 00 59 01011001 0.69 0 0e 00001110 0.315 34 00110100 0.505 5a 01011010 0.695 0f 00001111 0.32 0 35 00110101 0.51 0 5b 01011011 0.7 00 10 00010000 0.325 36 00110110 0.515 5c 01011100 0.705 11 00010001 0.33 0 37 00110111 0.52 0 5d 01011101 0.71 0 12 00010010 0.335 38 00111000 0.525 5e 01011110 0.715 13 00010011 0.34 0 39 00111001 0.53 0 5f 01011111 0.72 0 14 00010100 0.345 3a 00111010 0.535 60 01100000 0.725 15 00010101 0.35 0 3b 00111011 0.54 0 61 01100001 0.73 0 16 00010110 0.355 3c 00111100 0.545 62 01100010 0.735 17 00010111 0.36 0 3d 00111101 0.55 0 63 01100011 0.74 0 18 00011000 0.365 3e 00111110 0.555 64 01100100 0.745 19 00011001 0.37 0 3f 00111111 0.56 0 65 01100101 0.75 0 1a 00011010 0.375 40 01000000 0.565 66 01100110 0.755 1b 00011011 0.38 0 41 01000001 0.57 0 67 01100111 0.76 0 1c 00011100 0.385 42 01000010 0.575 68 01101000 0.765 1d 00011101 0.39 0 43 01000011 0.58 0 69 01101001 0.77 0 1e 00011110 0.395 44 01000100 0.585 6a 01101010 0.775 1f 00011111 0.4 00 45 01000101 0.59 0 6b 01101011 0.78 0 20 00100000 0.405 46 01000110 0.595 6c 01101100 0.785
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 22 vid7:vid0 (hex) vid 7:vid0 ( bin ) voltage vid7:vid0 (hex) vid 7:vid0 ( bin ) voltage vid7:vid0 (hex) vid 7:vid0 ( bin ) voltage 21 00100001 0.41 0 47 01000111 0.6 00 6d 01101101 0.79 0 22 00100010 0.415 48 01001000 0.605 6e 01101110 0.795 23 00100011 0.42 0 49 01001001 0.61 0 6f 01101111 0.8 00 24 00100100 0.425 4a 01001010 0.615 70 01110000 0.805 25 00100101 0.43 0 4b 01001011 0.62 0 71 01110001 0.81 0 72 01110010 0.815 99 10011001 1.01 0 c0 11000000 1.205 73 01110011 0.82 0 9a 10011010 1.015 c1 11000001 1.21 0 74 01110100 0.825 9b 10011011 1.02 0 c2 11000010 1.215 75 01110101 0.83 0 9c 10011100 1.025 c3 11000011 1.22 0 76 01110110 0.835 9d 10011101 1.03 0 c4 11000100 1.225 77 01110111 0.84 0 9e 10011110 1.035 c5 11000101 1.23 0 78 01111000 0.845 9f 10011111 1.04 0 c6 11000110 1.235 79 01111001 0.85 0 a0 10100000 1.045 c7 11000111 1.24 0 7a 01111010 0.855 a1 10100001 1.05 0 c8 11001000 1.245 7b 01111011 0.86 0 a2 10100010 1.055 c9 11001001 1.25 0 7c 01111100 0.865 a3 10100011 1.06 0 ca 11001010 1.255 7d 01111101 0.87 0 a4 10100100 1.065 cb 11001011 1.26 0 7e 01111110 0.875 a5 10100101 1.07 0 cc 11001100 1.265 7f 01111111 0.88 0 a6 10100110 1.075 cd 11001101 1.27 0 80 10000000 0.885 a7 10100111 1.08 0 ce 11001110 1.275 81 10000001 0.89 0 a8 10101000 1.085 cf 11001111 1.28 0 82 10000010 0.895 a9 10101001 1.09 0 d0 11010000 1.285 83 10000011 0.9 00 aa 10101010 1.095 d1 11010001 1.29 0 84 10000100 0.905 ab 10101011 1.1 00 d2 11010010 1.295 85 10000101 0.91 0 ac 10101100 1.105 d3 11010011 1.3 00 86 10000110 0.915 ad 10101101 1.11 0 d4 11010100 1.305 87 10000111 0.92 0 ae 10101110 1.115 d5 11010101 1.31 0 88 10001000 0.925 af 10101111 1.12 0 d6 11010110 1.315 89 10001001 0.93 0 b0 10110000 1.125 d7 11010111 1.32 0 8a 10001010 0.935 b1 10110001 1.13 0 d8 11011000 1.325 8b 10001011 0.94 0 b2 10110010 1.135 d9 11011001 1.33 0 8c 10001100 0.945 b3 10110011 1.14 0 da 11011010 1.335 8d 10001101 0.95 0 b4 10110100 1.145 db 11011011 1.34 0 8e 10001110 0.955 b5 10110101 1.15 0 dc 11011100 1.345
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 23 vid7:vid0 (hex) vid 7:vid0 ( bin ) voltage vid7:vid0 (hex) vid 7:vid0 ( bin ) voltage vid7:vid0 (hex) vid 7:vid0 ( bin ) voltage 8f 10001111 0.96 0 b6 10110110 1.155 dd 11011101 1.35 0 90 10010000 0.965 b7 10110111 1.16 0 de 11011110 1.355 91 10010001 0.97 0 b8 10111000 1.165 df 11011111 1.36 0 92 10010010 0.975 b9 10111001 1.17 0 e0 11100000 1.365 93 10010011 0.98 0 ba 10111010 1.175 e1 11100001 1.37 0 94 10010100 0.985 bb 10111011 1.18 0 e2 11100010 1.375 95 10010101 0.99 0 bc 10111100 1.185 e3 11100011 1.38 0 96 10010110 0.995 bd 10111101 1.19 0 e4 11100100 1.385 97 10010111 1 .000 be 10111110 1.195 e5 11100101 1.39 0 98 10011000 1.005 bf 10111111 1.2 00 e6 11100110 1.395 e7 11100111 1.4 00 f0 11110000 1.445 f9 11111001 1.49 0 e8 11101000 1.405 f1 11110001 1.45 0 fa 11111010 1.495 e9 11101001 1.41 0 f2 11110010 1.455 fb 11111011 1.5 00 ea 11101010 1.415 f3 11110011 1.46 0 fc 11111100 1.505 eb 11101011 1.42 0 f4 11110100 1.465 fd 11111101 1.51 0 ec 11101100 1.425 f5 11110101 1.47 0 fe 11111110 1.515 ed 11101101 1.43 0 f6 11110110 1.475 ff 11111111 1.52 0 ee 11101110 1.435 f7 11110111 1.48 0 ef 11101111 1.44 0 f8 11111000 1.485
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 24 adaptive voltage pos itioning adaptive voltage positioning (avp) is a control algorithm where the output voltage is reduced as the load current increases. this may also be referred to as vr output impedance, voltage droop or load line. a vp is implemented to reduce the amount of bulk capacitance for a given load transient and regulation window and reduces po wer dissipation at heavy load. the ir 3531a implementation of voltage positioning for rail0 and rail1 is shown in figure 10 . the outp ut voltage is set by the vdac or track reference voltage at the positive input of the error amplifier. inductor dcr tempera ture compensation the load current information for all the phases is fed back to the control ic through the driver ic iout pins where this information is averaged and buffered to the thermal compensation amplifier. the gain of the thermal compensation amplifier is modified by temperature by introducing a negative temperature coef ficient (ntc) thermistor (rt herm 1) and linearizing resistor network (rtcmp1 and 2) connected between the vn and vdrp pins. the thermistor should be placed close to the power stage to accurately sense the thermal performance of the inductor dcr. the vdrp pin is connected to the fb pin th rough the resistor rdrp. as load current increases, the vdrp voltage increases proportionally. since the error amplifier will force the loop to maintain fb to be equal to the vdac reference voltage, the additional rdrp current has to flow through the rfb r esistor which introduces an offset voltage that is pro portional to the load current. the rfb current is equal to (vdrp - vdac)/ rdrp. the positioning voltage can be programmed by the resistors rdrp and rfb so that the droop impedance produces the desired conv erter output impedance. the offset and slope of the converter output impedance are referenced to and therefore independent of the vdac voltage . current monitor (imo n) the control ic generates a current monitor signal imon using the vdrp voltage and the vda c reference, a l s o shown in figure 10 . the voltage at this pin reports the average load current information referenced to lgnd . the slope of the imon signal with respect to the load current can be adjusted with the resistors rtcmp2 and rtcmp3. the imon sig nal is clamped at 1.0 9 v in order to facilitate direct interfacing with the master . figure 10 : adaptive voltage positioning with thermal compensation
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 25 remote voltage sensi ng the remote sense differential amplifier in the ir 3531a is a high speed, low input offset unity gain buffer that provides accurate voltage sensing and fast transient response. v osen+ and vosen - are the remote - sensing kelvin connections that are tied directly to the load. internal resistors to th e differential amplifier produce vosen+ and vosen - bias currents of up to 50 a maximum and limits the size series resistors for acceptable regulation of the output voltage. open sense lead detection is also included in this amplifier and is discussed furth er in the fault section . phase shedding ir 3531a allows phases to be disabled through the phsshed pin. shedding can be performed either statically at power up or can be exercised dynami cally during normal operation. one, two or three phases can be disabled to help enhance light load efficiency. the internal clock frequency is automatically adjusted to achieve graceful transition . phase shedding is not recommended if an external synchronization clock is being applied . t able 5: p hase s h edding p rogramming t hresholds threshold action phsshed < 0.25vcc no phases shed 0.25vcc < phsshed < 0.5vcc shed 1 phase 0.5vcc < phsshed < 0.75vcc shed 2 phases phsshed < 0.7 5vcc shed 3 phases power states and hig h efficiency mode at low loads system processors can request the vr to enter higher efficiency power savings mode s. the ir 3531a enters single phase operation when a ps1 command is issued from the processor. this mode is intended for loads less than 20a. there is an 8 switching cycle de lay before the vr transitions from ps0 to ps1. ps2 mode is not supported. platform test mode platform test mode allows users to test the vr solution when the default vboot voltage programmed on ir 3531a is 0v and there is no communication capability to send commands. the address pin needs to be pulled up to 3.3v for ir 3531a to go into platform test mode. ir 3531a will boot to 1v in this mode . protection the fault table below describes the different faults that can occur and how the ir 3 531a reacts to protect the supply and the load from possible damage. the fault types that can occur are listed in row 1. row 2 has the method that a fault is cleared. the first 3 faults are latched in the uv fault latch and the vcc power has to be recycled to clear. an over voltage fault can be cleared by recycling either vcc or the enable signal. the rest of the faults (except for uvlo vout and svid faults) are temporarily latched in the ss fault latch until the fault condition clears. most faults disable the error amplifier (except for svid and vout uvlo). most faults (except svid) flag vrrdy. vrrdy returns to active high when all faults are cleared. the delay row shows reaction time after detecting a fault condition. delays are provided to minimize the po ssibility of nuisance faults. the table applies for both rails of the ic .
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 26 t able 6 : f ault o peration fault type open control loop open sense line over voltage over current svid enable low v12v uvlo vcc uvlo vo uvlo fault clearing method recycle vcc or enable resume normal operation when condition clears error amp disabled yes no yes , after softstop no rosc/ovp drives high until ov clears no yes no vrrdy low? yes no yes vdac response? transition to 250mv and holds until fault is cleared no change if fault occurs on rail0 will rail1 continue to operate? no no no no yes no no no yes if fault occurs on rail1 will rail0 continue to operate? no no no no yes no no no yes delay 8 pwm cycles no no 256s 4 svid clock cycles to send nak 250 ns blank time no no no enable input the enable pin has a 0.6v falling threshold that sets the fault latch, a 650mv rising threshold that clears the fault latch and has a 250ns filter to prevent chatter due to system noise. when clearing an oc fault latch, it is recommended to allow sufficient thermal relaxation time prior to repeat re - enabling to ensure the convert er does not thermally run away. approximately 4ms thermal relaxation is recommended for most designs . open voltage loop de tection if fo r some reason the control loop fails during operation, the system protects itself by latching an open loop fault that r equires vcc recycling to clear. detection is performed by monitoring the output of the error amplifier. the fault is latched if eaout op erates above vcc - 1.08v for 8 switching cycles indicating the control loop is broken. open remote sense li ne protection the vosen+ and vosen - remote sense line impedances are checked prior to power up to verify they ar e connected to low impedances. if high impedance is detected, an open sense line fault is latched and require s vcc to be recycled to clear. during normal operation, the remote sense amp operating environment is monitored to ensure the remote sense lines are connected. again, if an abnormal mode is detected, the sense line impedan ces are again checked. if high impedance is detected, an open sense line fault is latched and requi res vcc to be recycled to clear. v12 v and vcc under volt age lockout (uvlo) the ir 3531a monitors the convert er input voltage rails (v12v and vcc) and issues a uvlo fault if either voltage is belo w the desired operating range. the maximum power up clear thresholds are 10.2v for v12v and 6.2v for vcc .
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 27 voltage regulator re ady (vrrdy, v rrdy1) the vrrdy pins are an open - collector outputs w hich require external pull - ups. the pull down device is design to achieve 400mv while sinking 4ma and can sustain voltages up to 7.5v. a high vrrdy indicates the output voltage is in regulation and there are no system faults in the ir 3531a . vrrdy monitors the status of the output voltage with respect to either the track pin or vdac. during power up after enable is released, the output voltage will be monitored with respect to track - 200mv. vrrdy is held low until the internal vdac re aches its boot voltage of 1.5v which takes 300usec due to the 5mv/usec vdac slew rate. vrrdy is then allowed to go high if vo is within track - 200mv. this is true even if track=0v. vrrdy will be held low if vo is less than track - 200mv. figure 1 1 depicts v arious power - up scenarios: scenario 1: vrrdy is gated by vdac reaching vboot=1.5v. track and the regulated output voltage power up within 300 sec. scenario 2: vrrdy is still gated by vdac reaching vboot since vo is correctly following track. scenario 3: vo is unresponsive in this scenario. vrrdy will flag high as long as vo is within 200mv of track. once track exceeds vo by 200mv, vrrdy will flag low indicating a regulation fault. scenario 4: track - vo exceeds 200mv prior to vdac reaching boot resulting in vrrdy being consistently held low. scenario 5: a regulation failure occurs during (or even post) power up resulting in track - vo exceeds the 200mv uvlo threshold. the vo uvlo threshold returns to vdac - 290mv once a valid svid command slews vdac and vo regulates within 10mv of the final vdac transition voltage . track can then be transitioned to a voltage greater than vo+200mv without affecting vrrdy . figure 1 1 C vrrdy power - u p scenarios v d a c = 1 . 5 v 5 m v / u s e c t r a c k v o v r r d y s c e n a r i o 1 . t r a c k v d a c g a t e s v r r d y v d a c = 1 . 5 v 5 m v / u s e c t r a c k v o v r r d y s c e n a r i o 2 . t r a c k v d a c g a t e s v r r d y v d a c = 1 . 5 v 5 m v / u s e c t r a c k v o v r r d y = 0 s c e n a r i o 4 . u n r e s p o n s i v e v o p r i o r t o v d a c = 1 . 5 v v d a c = 1 . 5 v 5 m v / u s e c t r a c k v o v r r d y s c e n a r i o 3 . u n r e s p o n s i v e v o p o s t v d a c = 1 . 5 v 2 0 0 m v v d a c = 1 . 5 v 5 m v / u s e c t r a c k v o v r r d y s c e n a r i o 5 . v o f a i l u r e p o s t v d a c = 1 . 5 v 2 0 0 m v
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 28 start - up and shut - down sequence the ir 3531a has a programmable, digitally controlled soft - start function to limit the surge current during the voltage regulator start - up. the default boot voltage for rail0 rail is 1.5 v, for rail1 it i s 1.5v . figure 1 1 depicts an enable gated power - up and v12v uvlo shutdown followed by a v12v uvlo gated power up and an enable low shutdown. the ir 3531a requires less than 1ms to perform calibration routines once v12v (vin) uvlo is cleared. note vdac is forced to 1.52v during calibration and a/d sampling and settles to 250mv once calibration is complete . figure 1 2 shows two different power - up responses where enable going high is gating the firs t vdac slew and the calibration routine i s gating the second vdac slew. the default slew rate is 5mv/ sec. the control loop ensures the regulator output voltage will track vdac. the soft start sequence finishes when vout is settled to the vboot set point and vrrdy is asserted . the ir 3531a has soft stop capability which allows the voltage regulator to power down in a controlled fashion without producing negative undershoots resulting from fast di scharge of output capacitance. pre - biased outputs are also supported as shown in figure 1 3. figure 1 2 : v12v power and e nable c ycling figure 1 3 : enable power cycling under pre - bias v12v uvlo threshold vdac=0.9v 1.52v during pin program sensing 0v 250mv 1.52v during pin program sensing vdac=0.9v enable tmax=(1.52-0.25)/5mv=254usec allow 1msec after vin uvlo to allow a/d pin sensing and internal calibration routines to occur before attempting power-up. diode emulation not allowed diode emulation not allowed vout=>prebias vdac track vout= vdac vrrdy vdac enable vout=prebias 250mv
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 29 over - current control over current protection (ocp) is a latched event that requires vcc u vlo or enable cycling to clea r. ocp is performed internally by comparing the vdrp pin voltage against an oc offset voltage that is added to th e respective vdac pin voltage. this oc offset voltage is adjusted to match the active number of phases since vdrp represe nts average per - phase current. this ensures that the current limit is correctly adjusted during phase shedding operation. an over current condition is registered if the vdrp pin voltage, which is proportional to the average current plus vdac voltage, excee ds the vdac+ oc offse t voltage. figure 1 4 shows the over - current control with delay during various soft start events. a fixed 256s oc delay is needed to protect against nuisance over - current conditions which can occur as part of normal operation or due to inrush currents. enable or vcc uvlo cycling clears the ocp fault latch. it is recommended to allow sufficient thermal relaxation time prior to repeat re - enabling to ensure the converter does not thermally run away. approximately 4ms thermal relaxation i s recommended for m ost designs. if enable is cycled during this relaxation period, the converter will wait until the internal vdac has returned to 0v prior t o attempting another power up. the internal vdac slews at 5mv/ sec and therefore the rise and fall slew durations are 300 sec for a boot of 1.5v. the vdac pin slews down to 250mv and does not slew to 0v. this is done to ensure the current reporting system has enough headroom to properly operate. if an over - current occurs during soft start, the control ic will not disable the voltage regulator until the over current delay time has elapsed. if the over - current condition persists after delay time is reached, the fault latch will be set pulling the error amplifiers output low and inhibiting switching in the driver ics . figure 1 4 : over c urrent w av eforms i o u t o c p t h r e s h o l d v o u t i n t e r n a l v d a c t r a c k 2 5 6 u s o c d e l a y e n a b l e c y c l e d o e s n o t h a v e a n e f f e c t o n v o u t u n t i l v d a c h a s r e s e t t o 0 v . u s e r m u s t e n s u r e p r o p e r t h e r m a l r e l a x a t i o n h a s o c c u r r e d p r i o r t o r e - e n a b l i n g . e n a b l e e n a b l e c y c l e a f t e r a r e c o m m e n d e d 4 m s r e l a x a t i o n t i m e o u t v r r d y m o m e n t a r i l y g o e s h i g h o n c e v d a c r e a c h e s b o o t a n d t h e n f a u l t s o n c e t r a c k - v o u t e x c e e d s 2 0 0 m v . v r r d y v r r d y r e m a i n s l o w b e c a u s e t r a c k - v o u t e x c e e d s 2 0 0 m v p r i o r t o v d a c r e a c h i n g b o o t . v r r d y m o m e n t a r i l y g o e s h i g h o n c e v d a c r e a c h e s b o o t a n d t h e n f a u l t s o n c e t r a c k - v o u t e x c e e d s 2 0 0 m v . v d a c c o n t r o l s v o u t p o w e r u p w h e n t r a c k r e m a i n s h i g h r e c o m m e n d ~ 4 m s r e l a x a t i o n d e l a y v d a c p i n
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 30 iccp (icc max) progr amming svid register icc max contains information on the maximum allowable current supported by the voltage regulator solution and can be equivalent to the cpus icc_max. the cpu reads this register for platform com patibility during boot and uses this data in conjunction with the iout regist er for performance management. this data is in an 8 - bit binary formant equivalent to amps, i.e . 75a=4bh. the voltage is programmed by an external resistor divider string referenced to vdac. table 7 lists the available current thresholds t able 7: iccp (icc m ax ) a/d v oltage p rogramming ( as % of vdac) %vdac binary code current level 1.5 00000 60a/25a 4.7 00001 60a/35a 7.8 00010 70a/25a 11 00011 70a/35a 14 00100 80a/25a 17.2 00101 80a/35a 20.3 00110 90a/25a 23.4 00111 90a/35a 26.5 01000 100a/25a 29.7 01001 100a/35a 32.8 01010 110a/25a 36 01011 110a/35a 39 01100 120a/25a 42.2 01101 120a/35a 45.3 01110 130a/25a 48.4 01111 130a/35a 51.5 10000 140a/25a 54.7 10001 140a/35a 57.8 10010 150a/25a 61 10011 150a/35a 64 10100 160a/25a 67.2 10101 160a/35a 70.3 10110 170a/25a 73.4 10111 170a/35a 76.6 11000 180a/25a 79.7 11001 180a/35a 82.8 11010 190a/25a 86 11011 190a/35a 89 11100 200a/25a 92.2 11101 200a/35a 95.3 11110 225a/25a 98.4 11111 225a/35a temperature telemetr y the maximum temperature tmax (22h) value is factory programmed to 11 0c. this register contains the maximum temperature the vr supports prior to issuing a thermal alert or vr_hot. the master reads this register and uses this data in conjunction with the temperature zone s for performance management. factory trim options are list ed in table 8 . t able 8 : t emp m ax (p rogrammed at f inal t est ) binary code temperature binary code temperature 000 90 deg c 100 106 deg c 001 94 deg c 101 110 deg c 010 98 deg c 110 114 deg c 011 102 deg c 111 118 deg c thermal monitoring ( vrhot#) the ir 3531a provides two methods of thermal monitoring: a vrhot# pin which flags an over temperature event and temperature telemetry is available through the svid bus and the temperature zone register. a thermal sense network which includes an ntc thermistor provides board temperature information at tsens pin as shown in figure 1 5 . the thermistor is usually placed in a temperature sensitive region of the converter and is linearized by a resistor network. vrhot# will be active low once the voltage on tsens crosses zone 7, or 56.3% of vdac. vrhot# will de - assert once tsens falls below zone 5. the vrhot# pin is an open - collector output and should be pulled up to a voltage source through a resistor . figure 1 5 : over temperature detection circuit the ir 3531a compares the tsens pin voltage against fixed percentages of vdac thresholds as indicated in table 9. the user can program the external tsens network to achieve a desired offset and slope to associate a zone (stored in register 12h) with a desired temperatu re. vdac vdac vrhot# tsens rtherm2 + - rhotset1 rhotset2 rhotset3 control ic zone 5: 53.1% zone 7: 56.3%
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 31 zones corresp ond to the bit number of this 8 - bit register, i.e. zone 0=bit 0 and zone 3=bit3 and therefore register 1 2h behaves like a thermometer. notice that the zones 1 through 7 thresholds are equally spaced (~1.6% between thresholds) and the separation between zone0 and zone1 is approximately double. since these zone thresholds are fixed and equally separated, the respective zone temperature valu es will also be equally separated for a tsens voltage which has a linear slope vs. temperature. the svid status register bit#1 and the alert# serve as thermal warning flags when zones 5 and 6 are c rossed as indicated in table 9. these warning flags may be used by the system to reduce the load, increase airflow, and prevent the system from entering thermal shutdown. the vrhot# pin is asserted as zones 6 and 7 are crossed and can be used as a thermal shutdown flag. tmax is mere ly a reference point to communicate with downstream system monitors what temperature a zone equates to. for example, the tmax register is defaulted in the ir 3531a as 110c. the micro processor can perform a getreg on tmax and is now able to associate a zon e 4 declaration by the ir 3531a to equate to 100.1c t able 9: t emperature z ones temperature zone tsens threshold % vdac % of tmax degrees c based on 110c tmax zone 0 43.8% 75% 82.5c zone 1 46.9% 82% 90.2 zone 2 48.4% 85% 93.5 zo ne 3 50% 88% 96.8 zone 4 51.6% 91% 100.1 falling, status bit 1 de - asserted, alert#. zone 5 53.1% 94% 103.4 falling, vrhot# de - asserted zone 6 54.7% 97% 106.7 rising, status bit 1 asserted, alert#. zone 7 56.3% 100% 110 rising, vrhot# asserted over voltage protection ( ovp) the ir 3531a offers multilevel output over - voltage protection to ensure no conflicts occur during pre - biased conditioned power - up or no/light load soft stop. ovp is sensed through the fb which allows users to externally use fb resis tor dividers if output voltages greater than 1.52v are desired. the ovp threshold is set to 1.65v during power up until vr settled is reached, then the thre shold is reduced to vdac+130mv. this ovp threshold is maintained during normal operation and remains until vo, the output of the remote sense amplifier, reaches 250mv with respect to ground. this ensures ovp protection during soft stop events or d own tracking events. the ovp threshold then returns to 1.65v on the fb pin to allow pre - bias startup. ir 3531a drive s the rosc/ovp pin above v(vcc) C 1v to indicate an over v oltage event has occurred. this rosc/ ovp flag can be used by the system designer to shut the input if desired. the over voltage condition also sets the over voltage fault latch which ensures the voltage regulator is off . ovp overrides the normal pwm operation and will regulate the output voltage by modulating the low side mosfet within approximately 150ns to prevent the fb pin from exceeding the ovp threshold. the ovp fault condition can only be cleared by cycling vcc uvlo or enable . figure 1 6 : over v oltage p rotection during setvid fast/slow vid down normal operation vdac ov threshold vdac + 130mv vid up normal operation vid low vdac + 130mv
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 32 design procedures ir 3531a external components switching frequency setting use the sclk input to set pwm frequency. rosc should be present, and selected for the per phase switching frequency in use. the chart below shows the re lationship between the per - phase switching frequency and the rosc value . figure 1 7 : rrosc vs. per - phase switching frequency address and pha se number programmin g resistors raddr1 and raddr2 the addr pin allows for the selection of the svid address for rail0 and rail1 . choose raddr2 and apply the following equation to determine raddr1 . where, %vdac is the desired percentage of vdac found in table 1. iccp programming res istors riccp1 and riccp2 the iccp programming resistors are used to program the maximum currents rail0 and rail1 can support. choose riccp2 and fol low the equation below to calculate riccp1 . where, %vdac is the desired percentage of vdac found in table 7. phase shedding imple mentation circuits the following is a proposed circuit to implement phase shedding. two signals (s1 and s2) drive logic level mosfets to produce a four level phsshed signal. the operation is described in table 6 . figure 1 8 : phase shedding implementation t able 10 : p hase shedding control s1 s2 v(phsshed) phases 0 0 vcc drop 3 phases 0 1 0.625* vcc drop 2 phases 1 0 0.31* vcc drop 1 phases 1 1 0v drop 0 phases imon and imon1 capac itors use 100 nf for cimon and cimon1 to provide an approximate 1ms filtered time constant for current reporting data. vcc bias regulator power stag e components use a 10 h inductor with a current rating no less than 2 a. use a schottky diode with operating current of 1 a or higher and capable of withstanding 2 a for short periods of time. a 10 f capacitor ceramic capacitor rated for 16v is recommended for charge storage and filtering. 2 * 100 * % 100 % 1 1 raddr vdac vdac raddr ? ? 2 * 100 * % 100 % 1 1 riccp vdac vdac riccp ? ?
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 33 temperature sensing the tsens pin is used to provide temperature information of the voltage regulator by providing temperature zone information to the mi croprocessor through the svid. this information is also used to flag vrhot#. temperature is sensed via a l inearized ntc resistor network. tempera - ture sensing and temperature zones are represented as a percentage of the reference voltage vdac as required by the processor specification. a properly design ed network will get the tsens voltage very close to the required target. 1% thermistors are highly recommended to a chieve the specified accuracy. thermistor beta is the biggest factor in attaining accuracy . the target and tsens voltages are calculated from the equations below . the analysis is done at vdac of 1.5, because that is where the biggest error occurs . where rtherm2 room is the thermistor value at room temperature, beta is the thermistor coefficient, tmax and tmin are the temperatures of the highest and lowest temperature zone respectively. the temperature sensing components are chosen by finding an appro ximate solution that brings the target and tsens as close to each other as possible. this can be done using an optimization routine of your choice such as the ir 3531a excel design tool. rail0 thermal compen sation thermal compensation is required to counter the effect of the inductor dcr positive temperature coefficient. failure to compensate results in large current reporting errors and poor load line regulation. thermal compensation is done using a ntc thermistor and a linearizing resistor network. a prope rly design network is necessary to achieve the required accuracy targets. 1% thermistors are highly recommended to achieve the specified accuracy. thermistor beta is the biggest factor in attaining accuracy. the goal is to keep vdrp - vdac at 900 mv for a ll temperatures a t the maximum current. thus, the equation below has to be satisfied . where rtherm1 room is the thermistor value at room temperature, beta is the thermistor coefficient, tmax and tmin are the temperatures of the highest and lowest temperature zone respectively, gcs is the typical current sense amplifier gain of 32.5, and dcr room is the induct or series resistance at room temperature. the temperature sensing components are chosen by finding an approximate solution that results in vdrp - vdac=900mv over the entire temperature operating range. this can be done using an optimization routine of your c hoice such as the ir 3531a excel design tool . rail0 droop resistor calculation rdrp in combination with the feedback resistor rfb sets the load line of rail0. rfb is first chosen with a typical suggest ed value of 2kohm. the following equation calculates rdr p . where ro is the load line, dcr room is the inductor series resistance at room temperature, gcs is the typical current sense amplifier gain of 32.5, n is the number of phases and rtceq room is the same as rtceq in section rail0 therm al compensation with rtherm1 value at room temperature . min * min max 5 . 1 * 11 . 0 5 . 1 * 453 . 0 * min max 5 . 1 * 11 . 0 t t t t t t v target ? ? ? ? ? 5 . 1 * 3 3 rtseq rhotset rhotset v tsense ? ? 2 2 1 2 * ) 2 1 ( rtherm rhotset rhotset rhotset rtherm rhotset rtseq ? ? ? ? )) 1 1 ( exp( * 2 2 room room t t beta rtherm rtherm ? ? mv ax rtcmp rtceq n gcs dcr vdac vdrp 900 im * ) 3 1 ( * ) * ( * 3 1 ? ? ? ? 1 2 1 ) 1 1 ( * 2 rtherm rtcmp rtcmp rtherm rtcmp rtcmp rtceq ? ? ? ? )) 1 1 ( exp( * 1 1 room room t t beta rtherm rtherm ? ? )) ( * 6 3850 1 ( * room room t t e dcr dcr ? ? ? ? ) 3 1 ( * * * 3 * * rtcmp rtceq n ro gcs dcr rfb rdrp room room ? ?
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 34 rail1 thermal compen sation rscale1, rscale2 , rscale3 and rtherm3 are used to provide current reporting thermal compensation for rail1. the purpose is to keep vdrp1 - vdac1 equal to 900mv for all tempe ratures at the maximum load current. this is expresse d mathematically in the following equation. where dcr and rtherm3 are expressed in section rail0 thermal compensation. imax is the maximum current for rail1 and gcs is the typical current sense amplifier gain of 32.5. the temperature sensing components are chosen by finding an approximate solution that results in vdrp1 - vdac1=900mv over the entire temperature operating range. this can be done using an optimization rou tine of your choice such as the ir 3531a excel design tool . rail 1 droop resisto r calculation rdrp1 in combination with the feedback resistor rfb1 sets the load line of rail1. rfb1 is first chosen with a typical suggested value of 2kohm. the equation below calculates rdrp1 . where ro is the load line, dcr room is the inductor series resistance at room temperature, gcs is the typical current sense amplifier gain of 32.5, rtherm3 room value at room temperature . compensation network s ir 3531a utilizes voltage mode control for small signal loop regulation. the compensation scheme is a classic type 3 system consisting of components rfb(1), cfb(1), rcfb(1), cea(1), ccp(1) and rcp(1). the system dynamics can change significantly when transi tioning from 4 phases to 1 phase. loop 0 has an additional component, rpsc, that is inserted in the loop when in ps1 mode (single ph ase) to optimize phase margin. rpsc adds to rcp thereby reducing the system bandwidth if desired. t o disable this feature, p la ce rpsc as a zero ohm resistor. the ir 3531a excel design tool can be used to calculate an initial starting point. note rdrp needs to be recalculated if rfb is changed . layout guidelines ? vcc bias inductor lvcc must be close to sw pin. vcc bias bulk cap coutvcc must be located near lvcc and connections for coutvcc must be as short as possible. ? for both rails, all components connected to ea, fb, vdrp, and vo pins must be located on the same layer as the ir3531a as close to these pins as possible. ? insert 9 equally spaced co nnection vias to gnd tab of ir3531a. ? v12v decoupling cap must be near pin of ir3531a with gnd connection as short as possible. ? rosc must be located close to pin of ir3531a. ? rtherm1 and rtherm3 must be located close to inductor of associat ed voltage regulator. locate rtherm2 to provide overall temperature reading of the power converter. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 3 1 3 * ) 3 1 2 3 3 1 3 * ) 3 1 ( * * * 1 * 9 1 rscale rtherm rscale rscale rtherm rscale rscale rscale rtherm rscale rscale rtherm rscale ro gcs dcr rfb rdrp room room room room room mv rscale rtherm rscale rscale rtherm rscale rscale rscale rtherm rscale rscale rtherm rscale ax gcs dcr vdac vdrp 900 3 3 1 3 * ) 3 1 ( 2 3 3 1 2 * ) 3 1 ( * im * * * 9 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 35 metal and component placement ? lead land width should be equ al to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to minimize prevent shorting. ? lead land length should be equal to maximum part lead length + 0.3 mm outboard extensi on + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extensi on will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maxi mum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. co pper and 0.23mm for 3 oz. copper) ? a single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the ic . ? no pcb traces should routed nor vias placed under any of the 4 corners of the ic package. doing so can cause the ic to r ise up from the pcb resulting in poor solder joints to the ic leads. figure 1 9 : metal and c omponent p lacement * contact i nternational r ectifier to receive an electronic pcb library file in your preferred format .
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 36 solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resist mi salignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist miss - alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in - between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. ? the vias in the large center pad should be tented or plugged from bottom board side with solder resist. figure 20 : solder r esist * contact i nternational r ectifier to receive an electronic pcb library file in your preferred format .
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 37 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the stencil lead land apertures should the refore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be approximately 70% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the sold er paste. . figure 21 : stencil d esign * contact i nternational r ectifier to receive an electronic pcb library file in your preferred format .
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 38 marking information figure 22 : package marking p ackage information 48l mlpq (7 x 7 mm body) ja = 2 3 . 5 oc/w, jc = 1 oc/w figure 23 : package d imensions 3531a ? yww ? xxxxx site/date/ marking code lot code
4+1 phase dual output control ic ir3531a march 22 , 2012 | final | v1.11 39 data and specifications subject to change without notice. this product will be designed and qualified for the consumer market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information . www.irf.com

▲Up To Search▲

Price & Availability of IR3531A-MTRPBF

	To Download IR3531A-MTRPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .